Activity: Academic Talks or Presentations › Keynote › Research
towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects (wireline), alternative interconnect fabrics such as inhomogeneous three-dimensional integrated Network-on-Chip (3D NoC) and hybrid wired-wireless Network-on-Chip (WiNoC) have emanated as a cost-effective solution for emerging System-on-Chip (SoC) design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power-hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in chip multiprocessor (CMP) demands an on-chip communication infrastructure which can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this talk, we explore a low-latency and low-complexity mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. A mechanism that incorporates a router that transmits flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads will be explored. Also, hybrid NoCs such as 3D NoCs, Wireless NoC (WiNoCs), Surgace wave WiNoCs will be explored to identify innovations and potential opportunities towards the continuity of advancing multicore technology for Emerging Computer Architectures.
26 Jan 2021
2021 International Conference on Big Data Analysis and Computer Science