A Study of Techniques to Increase Instruction Level Parallelisms

Liliana Margarita  Espinosa Jimenez; Michael Opoku Agyeman

doi:10.1145/3284557.3284562

A Study of Techniques to Increase Instruction Level Parallelisms

Liliana Margarita Espinosa Jimenez, Michael Opoku Agyeman

Computing

Research output: Contribution to Book/Report › Conference Contribution › peer-review

Abstract

Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.

Original language	English
Title of host publication	ISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control
Publisher	Association for Computing Machinery (ACM)
Pages	1-5
Number of pages	5
Volume	41
ISBN (Print)	978-1-4503-6628-1
DOIs	https://doi.org/10.1145/3284557.3284562
Publication status	Published - 21 Sept 2018
Event	2nd International Symposium on Computer Science and Intelligent Control - Stockholm, Sweden Duration: 21 Sept 2018 → 23 Sept 2018

Conference

Conference	2nd International Symposium on Computer Science and Intelligent Control
Country/Territory	Sweden
City	Stockholm
Period	21/09/18 → 23/09/18

Keywords

architectures
complex instruction
set computing
high performance
instruction level parallelism
parallel architectures
pipelines computing
pipelining
reduced instruction set computing
serial architectures
superscaler architectures
very long instruction word
vliw

Access to Document

10.1145/3284557.3284562

Cite this

@inproceedings{c650010eb9444297a950c7e414e79118,

title = "A Study of Techniques to Increase Instruction Level Parallelisms",

abstract = "Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.",

keywords = "architectures, complex instruction, set computing, high performance, instruction level parallelism, parallel architectures, pipelines computing, pipelining, reduced instruction set computing, serial architectures, superscaler architectures, very long instruction word, vliw",

author = "{Espinosa Jimenez}, {Liliana Margarita} and Agyeman, {Michael Opoku}",

year = "2018",

month = sep,

day = "21",

doi = "10.1145/3284557.3284562",

language = "English",

isbn = "978-1-4503-6628-1",

volume = "41",

pages = "1--5",

booktitle = "ISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control",

publisher = "Association for Computing Machinery (ACM)",

address = "United States",

note = "2nd International Symposium on Computer Science and Intelligent Control ; Conference date: 21-09-2018 Through 23-09-2018",

}

Espinosa Jimenez, LM & Agyeman, MO 2018, A Study of Techniques to Increase Instruction Level Parallelisms. in ISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control. vol. 41, Association for Computing Machinery (ACM), pp. 1-5, 2nd International Symposium on Computer Science and Intelligent Control , Stockholm, Sweden, 21/09/18. https://doi.org/10.1145/3284557.3284562

A Study of Techniques to Increase Instruction Level Parallelisms. / Espinosa Jimenez, Liliana Margarita ; Agyeman, Michael Opoku.
ISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control. Vol. 41 Association for Computing Machinery (ACM), 2018. p. 1-5.

Research output: Contribution to Book/Report › Conference Contribution › peer-review

TY - GEN

T1 - A Study of Techniques to Increase Instruction Level Parallelisms

AU - Espinosa Jimenez, Liliana Margarita

AU - Agyeman, Michael Opoku

PY - 2018/9/21

Y1 - 2018/9/21

N2 - Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.

AB - Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.

KW - architectures

KW - complex instruction

KW - set computing

KW - high performance

KW - instruction level parallelism

KW - parallel architectures

KW - pipelines computing

KW - pipelining

KW - reduced instruction set computing

KW - serial architectures

KW - superscaler architectures

KW - very long instruction word

KW - vliw

U2 - 10.1145/3284557.3284562

DO - 10.1145/3284557.3284562

M3 - Conference Contribution

SN - 978-1-4503-6628-1

VL - 41

SP - 1

EP - 5

BT - ISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control

PB - Association for Computing Machinery (ACM)

T2 - 2nd International Symposium on Computer Science and Intelligent Control

Y2 - 21 September 2018 through 23 September 2018

ER -

A Study of Techniques to Increase Instruction Level Parallelisms

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this