A study of techniques to increase Instruction Level Parallelism

Liliana Margarita Espinosa Jimenez, Michael Opoku Agyeman

Research output: Contribution to Book/Report typesChapter

Abstract

Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.
Original languageEnglish
Title of host publicationInternational Symposium on Computer Science and Intelligent Control
Place of PublicationSweden
PublisherISCSIC
Publication statusAccepted/In press - 20 Apr 2018

Fingerprint

Clocks
Microprocessor chips
Hardware

Keywords

  • Instruction Level Parallelism
  • high performance
  • VLIW
  • pipelining

Cite this

Espinosa Jimenez, L. M., & Opoku Agyeman, M. (Accepted/In press). A study of techniques to increase Instruction Level Parallelism. In International Symposium on Computer Science and Intelligent Control Sweden: ISCSIC.
Espinosa Jimenez, Liliana Margarita ; Opoku Agyeman, Michael. / A study of techniques to increase Instruction Level Parallelism. International Symposium on Computer Science and Intelligent Control. Sweden : ISCSIC, 2018.
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keywords = "Instruction Level Parallelism, high performance, VLIW, pipelining",
author = "{Espinosa Jimenez}, {Liliana Margarita} and {Opoku Agyeman}, Michael",
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Espinosa Jimenez, LM & Opoku Agyeman, M 2018, A study of techniques to increase Instruction Level Parallelism. in International Symposium on Computer Science and Intelligent Control. ISCSIC, Sweden.

A study of techniques to increase Instruction Level Parallelism. / Espinosa Jimenez, Liliana Margarita ; Opoku Agyeman, Michael.

International Symposium on Computer Science and Intelligent Control. Sweden : ISCSIC, 2018.

Research output: Contribution to Book/Report typesChapter

TY - CHAP

T1 - A study of techniques to increase Instruction Level Parallelism

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AU - Opoku Agyeman, Michael

PY - 2018/4/20

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AB - Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.

KW - Instruction Level Parallelism

KW - high performance

KW - VLIW

KW - pipelining

M3 - Chapter

BT - International Symposium on Computer Science and Intelligent Control

PB - ISCSIC

CY - Sweden

ER -

Espinosa Jimenez LM, Opoku Agyeman M. A study of techniques to increase Instruction Level Parallelism. In International Symposium on Computer Science and Intelligent Control. Sweden: ISCSIC. 2018