A Study of Techniques to Increase Instruction Level Parallelisms

Liliana Margarita Espinosa Jimenez, Michael Opoku Agyeman

Research output: Contribution to Book/ReportConference Contribution

Abstract

Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.
Original languageEnglish
Title of host publicationISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control
PublisherACM Press
Number of pages5
Volume41
ISBN (Print)978-1-4503-6628-1
DOIs
Publication statusPublished - 21 Sep 2018

Keywords

  • architectures
  • complex instruction
  • set computing
  • high performance
  • instruction level parallelism
  • parallel architectures
  • pipelines computing
  • pipelining
  • reduced instruction set computing
  • serial architectures
  • superscaler architectures
  • very long instruction word
  • vliw

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    Espinosa Jimenez, L. M., & Agyeman, M. O. (2018). A Study of Techniques to Increase Instruction Level Parallelisms. In ISCSIC '18 Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control (Vol. 41). ACM Press. https://doi.org/10.1145/3284557.3284562