A survey of low power design techniques for last level caches

Emmanuel Ofori-Attah, Xiaohang Wang, Michael Opoku Agyeman

Research output: Contribution to JournalArticle

Abstract

The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.
Original languageEnglish
JournalLecture Notes in Computer Science
Volume10824
DOIs
Publication statusPublished - 8 Apr 2018

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