A survey of low power design techniques for last level caches

Research output: Contribution to JournalArticle

Abstract

The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.
Original languageEnglish
JournalLecture Notes in Computer Science
Volume10824
DOIs
Publication statusPublished - 8 Apr 2018

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Electric power utilization
Budget control
Transistors

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@article{a1f04aafc4e4477da22d1d4488ba840c,
title = "A survey of low power design techniques for last level caches",
abstract = "The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.",
author = "Emmanuel Ofori-Attah and Xiaohang Wang and {Opoku Agyeman}, Michael",
year = "2018",
month = "4",
day = "8",
doi = "10.1007/978-3-319-78890-6_18",
language = "English",
volume = "10824",
journal = "Lecture Notes in Computer Science",
issn = "0302-9743",
publisher = "Springer Verlag",

}

A survey of low power design techniques for last level caches. / Ofori-Attah, Emmanuel; Wang, Xiaohang; Opoku Agyeman, Michael.

In: Lecture Notes in Computer Science, Vol. 10824, 08.04.2018.

Research output: Contribution to JournalArticle

TY - JOUR

T1 - A survey of low power design techniques for last level caches

AU - Ofori-Attah, Emmanuel

AU - Wang, Xiaohang

AU - Opoku Agyeman, Michael

PY - 2018/4/8

Y1 - 2018/4/8

N2 - The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.

AB - The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.

UR - http://www.springer.com/series/558

UR - http://arc2018.esda-lab.cied.teiwest.gr/

U2 - 10.1007/978-3-319-78890-6_18

DO - 10.1007/978-3-319-78890-6_18

M3 - Article

VL - 10824

JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

SN - 0302-9743

ER -