TY - JOUR
T1 - A survey of low power design techniques for last level caches
AU - Ofori-Attah, Emmanuel
AU - Wang, Xiaohang
AU - Opoku Agyeman, Michael
PY - 2018/4/8
Y1 - 2018/4/8
N2 - The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.
AB - The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.
UR - http://www.springer.com/series/558
UR - http://arc2018.esda-lab.cied.teiwest.gr/
U2 - 10.1007/978-3-319-78890-6_18
DO - 10.1007/978-3-319-78890-6_18
M3 - Article
SN - 0302-9743
VL - 10824
JO - Lecture Notes in Computer Science
JF - Lecture Notes in Computer Science
ER -