A survey of low power design techniques for last level caches

Emmanuel Ofori-Attah, Michael Opoku Agyeman, Xiaohang Wang

Research output: Contribution to conference typesPosterResearchpeer-review

Abstract

The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This posters presents a survey of recent contribution towards reducing power consumption in the LLC.
Original languageEnglish
Publication statusPublished - 2 May 2018
Event14th International Symposium on Applied Reconfigurable Computing (ARC 2018) - Santorini, Greece
Duration: 2 May 2018 → …

Conference

Conference14th International Symposium on Applied Reconfigurable Computing (ARC 2018)
Period2/05/18 → …

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Electric power utilization
Budget control
Transistors

Cite this

Ofori-Attah, E., Opoku Agyeman, M., & Wang, X. (2018). A survey of low power design techniques for last level caches. Poster session presented at 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), .
Ofori-Attah, Emmanuel ; Opoku Agyeman, Michael ; Wang, Xiaohang. / A survey of low power design techniques for last level caches. Poster session presented at 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), .
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author = "Emmanuel Ofori-Attah and {Opoku Agyeman}, Michael and Xiaohang Wang",
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Ofori-Attah, E, Opoku Agyeman, M & Wang, X 2018, 'A survey of low power design techniques for last level caches' 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), 2/05/18, .

A survey of low power design techniques for last level caches. / Ofori-Attah, Emmanuel; Opoku Agyeman, Michael; Wang, Xiaohang.

2018. Poster session presented at 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), .

Research output: Contribution to conference typesPosterResearchpeer-review

TY - CONF

T1 - A survey of low power design techniques for last level caches

AU - Ofori-Attah, Emmanuel

AU - Opoku Agyeman, Michael

AU - Wang, Xiaohang

PY - 2018/5/2

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N2 - The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This posters presents a survey of recent contribution towards reducing power consumption in the LLC.

AB - The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This posters presents a survey of recent contribution towards reducing power consumption in the LLC.

M3 - Poster

ER -

Ofori-Attah E, Opoku Agyeman M, Wang X. A survey of low power design techniques for last level caches. 2018. Poster session presented at 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), .