A survey of low power techniques for efficient Network-on-Chip design

Emmanuel Ofori-Attah, Michael Opoku Agyeman

Research output: Contribution to Book/ReportChapterpeer-review


Power consumption continues to be a challenge for designers as the complexity of NoC increases. The scaling down of technology towards the deep nanometer era will only cause an increase in the amount of power NoC components will consume. Therefore, low power design solution is one of the essential requirements of future NoC-based System-on-Chip (SoC) applications. Several techniques have been proposed over the years to improve the performance of the NoCs, trading-off power efficiency; particularly power hungry elements in NoC routers. Power dissipation can be reduced by optimizing the router elements, applying architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.
Original languageEnglish
Title of host publication23rd IEEE Symposium on High Performance Computer Architecture (HPCA)
Place of PublicationUSA
Publication statusAccepted/In press - 19 Dec 2016


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