A survey of power-aware Network-on-Chip design techniques

Research output: Contribution to JournalArticle

Abstract

The Network-on-Chip (NoC) paradigm has been heralded as the solution to the communication limitation that System-on-Chip (SoC) poses. As we usher into the billion-transistor era, NoC which was once deemed as the solution is defecting due to its power demanding components. Several techniques have been proposed over the years to improve the performance of the NoCs, trading off power efficiency. However, low power design solution is one of the essential requirements of future NoC- based SoC applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.
Original languageEnglish
JournalThe Thirteenth International Multi-Conference on Computing in Global Information Technology
Publication statusAccepted/In press - 30 Apr 2018

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Routers
Telecommunication links
Energy dissipation
Transistors
Network-on-chip
Communication
System-on-chip

Cite this

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abstract = "The Network-on-Chip (NoC) paradigm has been heralded as the solution to the communication limitation that System-on-Chip (SoC) poses. As we usher into the billion-transistor era, NoC which was once deemed as the solution is defecting due to its power demanding components. Several techniques have been proposed over the years to improve the performance of the NoCs, trading off power efficiency. However, low power design solution is one of the essential requirements of future NoC- based SoC applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.",
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AB - The Network-on-Chip (NoC) paradigm has been heralded as the solution to the communication limitation that System-on-Chip (SoC) poses. As we usher into the billion-transistor era, NoC which was once deemed as the solution is defecting due to its power demanding components. Several techniques have been proposed over the years to improve the performance of the NoCs, trading off power efficiency. However, low power design solution is one of the essential requirements of future NoC- based SoC applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.

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