Abstract
The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the architecture itself and the communication links. In this paper, a survey is conducted on recent contributions and techniques employed by researchers towards the reduction of power in the router architecture, network architecture and communication links.
| Original language | English |
|---|---|
| Title of host publication | IEEE Technically Sponsored Computing Conference 2017 |
| Place of Publication | London |
| Publisher | IEEE |
| Publication status | Accepted/In press - 14 Nov 2016 |
Keywords
- Network-on-chip
- communication links NoC
- formatting
- low power routerarchitecture
- virtual channel sharing