Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with many-core integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing eﬀorts try to overcome this challenge by activating nodes from diﬀerent parts of the chip at the expense of communication latency. Other eﬀorts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-oﬀ performance for power. We found out that, for a signiﬁcant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-oﬀ idle resources and integrating power saving materials.
|Number of pages
|EAI Endorsed Transactions on Industrial Networks and Intelligent Systems
|Published - 19 Sept 2018
- low power NoC architectures
- power budgeting