As we usher into the billion-transistor era, NoC which was once deemed as the solution is defecting due to high power consumption in its components. Several techniques have been proposed over the years to improve the performance of the NoCs, trading off power efficiency. However, low power design solution is one of the essential requirements of future NoC-based SoC applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.
|Title of host publication||International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC)|
|Place of Publication||Sweden|
|Number of pages||5|
|Publication status||Published - 25 Jan 2017|
- Low Power NoC
- 3D NoC
Ofori-Attah, E., & Opoku Agyeman, M. (2017). AISTECS '17 - Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems: A survey of low power NoC design techniques. In International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC) (pp. 22-27). ACM Press. https://doi.org/10.1145/3073763.3073767