To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.
|Title of host publication||2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)|
|Place of Publication||USA|
|Publication status||E-pub ahead of print - 9 Jan 2017|
Opoku Agyeman, M., & Zong, W. (2017). An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW) (pp. 79-84). IEEE. https://doi.org/10.1109/SBAC-PADW.2016.22