An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures

Keyphrases

• Router 100%
• Router Architecture 100%
• Network on chip 100%
• Chip-based 100%
• Three-dimensional (3D) 100%
• Integrated Network 100%
• Multicore Architecture 100%
• 3D Network-on-chip (3D NoC) 50%
• Average Packet Latency 25%
• Average Packet Delay 25%
• Technological Progress 25%
• Adaptive Router 25%
• Interconnect Fabric 25%
• Performance Optimization 25%
• Base Metals 25%
• Fast Pace 25%
• Low Latency 25%
• Traffic Load 25%
• Cost-effective Solution 25%
• Big Data Processing 25%
• Adaptive Routing 25%
• Performance Bottleneck 25%
• Performance Degradation 25%
• Exascale 25%
• Multicore Design 25%

Computer Science

• Networks on Chips 100%
• Router Architecture 100%
• Multi-Core Architectures 100%
• Average Packet Latency 50%
• Average Packet Delay 50%
• Effective Solution 50%
• Performance Degradation 50%
• Big Data Processing 50%
• Adaptive Routing 50%
• Performance Bottleneck 50%
• Fabric Interconnect 50%
• Multicore 50%