Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Michael Opoku Agyeman, Ali Ahmadinia, Nader Bagherzadeh

Research output: Contribution to JournalArticle

Abstract

Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound.
Original languageEnglish
Pages (from-to)103-117
Number of pages15
JournalJournal of Systems Architecture
Volume89
Early online date7 Aug 2018
DOIs
Publication statusPublished - Sep 2018

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Energy utilization
Routers
Costs
Electric power utilization
Network-on-chip
Communication
Hot Temperature

Keywords

  • Multi-core architectures
  • Network-on-Chip
  • 3D integration
  • 3D Integration

Cite this

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title = "Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip",
abstract = "Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound.",
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Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip. / Opoku Agyeman, Michael; Ahmadinia, Ali; Bagherzadeh, Nader.

In: Journal of Systems Architecture, Vol. 89, 09.2018, p. 103-117.

Research output: Contribution to JournalArticle

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AU - Ahmadinia, Ali

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