Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Computer Science

• Energy Consumption 100%
• Mapping Algorithm 100%
• Networks on Chips 100%
• Power Consumption 50%
• Many-Core 50%
• Core Architecture 50%
• Lower Energy Consumption 50%
• Experimental Result 50%
• Packet Delay 50%
• Branch-and-Bound Algorithm Design 50%
• Average Packet Latency 50%
• Manufacturing Cost 50%
• Traffic Pattern 50%

Keyphrases

• 3D Network-on-chip (3D NoC) 100%
• Application Mapping 100%
• Energy-aware 100%
• Performance-aware 100%
• Energy Consumption 25%
• Vertical Link 25%
• Mapping Algorithm 25%
• Router 25%
• NoCs 25%
• Many-core Architecture 12%
• Power Consumption 12%
• Three-dimensional Network-on-chip 12%
• High Complexity 12%
• Existing Algorithms 12%
• High Cost 12%
• Packet Delay 12%
• Manufacturing Cost 12%
• Branch-and-bound 12%
• Cost Performance 12%
• Traffic Pattern 12%
• Area Overhead 12%
• High Power 12%
• Low Power Consumption 12%
• High Density 12%
• Low Energy 12%
• Average Packet Latency 12%
• Thermal Issues 12%
• Area Consumption 12%
• Low Area 12%
• Real-time Traffic 12%