Heterogeneous 3D Network-on-Chip Architectures: Area and Power Aware Design Techniques

Michael Opoku Agyeman, Ali Ahmadinia, Alireza Shahrabi

Research output: Contribution to journalArticleResearchpeer-review

Abstract

Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.
Original languageEnglish
JournalJournal of Circuits, Systems and Computers
Publication statusPublished - 2013

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title = "Heterogeneous 3D Network-on-Chip Architectures: Area and Power Aware Design Techniques",
abstract = "Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5{\%}) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61{\%} and 19.7{\%}, respectively.",
author = "{Opoku Agyeman}, Michael and Ali Ahmadinia and Alireza Shahrabi",
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Heterogeneous 3D Network-on-Chip Architectures: Area and Power Aware Design Techniques. / Opoku Agyeman, Michael; Ahmadinia, Ali; Shahrabi, Alireza.

In: Journal of Circuits, Systems and Computers, 2013.

Research output: Contribution to journalArticleResearchpeer-review

TY - JOUR

T1 - Heterogeneous 3D Network-on-Chip Architectures: Area and Power Aware Design Techniques

AU - Opoku Agyeman, Michael

AU - Ahmadinia, Ali

AU - Shahrabi, Alireza

PY - 2013

Y1 - 2013

N2 - Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

AB - Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

M3 - Article

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

ER -