Low power heterogeneous 3D Networks-on-Chip architectures

Michael Opoku Agyeman, Ali Ahmadinia, Alireza Shahrabi

Research output: Contribution to Book/ReportChapter

Abstract

Three dimensional Network-on-Chip (3D NoC) architectures have evolved with a lot of interest to address the on-chip communication delays of modern SoC systems. In this paper we propose low power heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topologies. Experimental results show a negligible penalty of up to 5% in average packet latency of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers. The heterogeneity however provides superiority of up to 67% and 19.7% in total crossbar area and power efficiency of the NoC resources, respectively compared to that of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers.
Original languageEnglish
Title of host publicationProceedings of the 2011 International Conference on High Performance Computing and Simulation, HPCS 2011
Pages533-538
Number of pages6
DOIs
Publication statusPublished - 2011

Publication series

NameProceedings of the 2011 International Conference on High Performance Computing and Simulation, HPCS 2011

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Keywords

  • 3D-Integration
  • Multi-core Architectures
  • Networks-on-Chip

Cite this

Agyeman, M. O., Ahmadinia, A., & Shahrabi, A. (2011). Low power heterogeneous 3D Networks-on-Chip architectures. In Proceedings of the 2011 International Conference on High Performance Computing and Simulation, HPCS 2011 (pp. 533-538). (Proceedings of the 2011 International Conference on High Performance Computing and Simulation, HPCS 2011). https://doi.org/10.1109/HPCSim.2011.5999871