Three dimensional Network-on-Chip (3D NoC) is becoming increasingly popular to address the on-chip communication demands of modern multi-core systems. However, architectural framework of the 3D router uses more buffer resources than conventional 2D routers. Also, homogeneous 3D NoC topologies have more TSVs which have a costly and complex manufacturing process. To improve the performance and manufacturing cost in 3D NoCs we propose adaptive router architectures for heterogeneous and homogeneous 3D NoCs which combine both the area and performance benefits of static 2D and 3D router architectures. Experimental results show that with a negligible penalty of up to 0.4% in maximum operating frequency, we achieved performance improvement of up to 34% by replacing 2D static routers with adaptive routers in heterogeneous architectures.
|Title of host publication||Proceedings - 6th International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2011|
|Number of pages||6|
|Publication status||Published - 2011|
|Name||Proceedings - 6th International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2011|