Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation

Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in
three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which
impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require
more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area
and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer
from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource
usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical
connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and
generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore,
the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed
algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the
existing solutions.