Experimental results have shown that the Neutron and proton induced upset is the root cause of increasing the sensitivity of microelectronics to soft errors. Thus eliminating these errors are the main challenge to overcome while designing and implementing any microelectronic device, error detection and correction technologies are practical ways that could be applied to fulfill such a purpose. Hamming code, Reed-Solomon codes, Parity Matrix codes, and many more techniques, have been developed and used over the last decades targeting memory protection. Which are still delivering qualified performance measures; however, the downside of these approaches is that they necessitate more redundant memory space, transmission delay, and sophisticated reliability architecture. This paper highlights various memory protection technologies, particularly emphasizing on The Decimal matrix code (DMC) with Encoder Reuse Technique (ERT).
|Publication status||Accepted/In press - 9 Apr 2019|
|Event||International Symposium on Computer Science and Intelligent Control - Amsterdam, Netherlands|
Duration: 25 Sep 2019 → 27 Sep 2019
|Conference||International Symposium on Computer Science and Intelligent Control|
|Abbreviated title||ISCSIC 2019|
|Period||25/09/19 → 27/09/19|
Zenki, R., & Opoku Agyeman, M. (Accepted/In press). Protection of Memory Using Code Redundancies: A Brief Study. Paper presented at International Symposium on Computer Science and Intelligent Control, Amsterdam, Netherlands. https://doi.org/10.1145/3386164.3386167