SlideAcross: a low-latency adaptive router for chip multi-processor

Wen Zong, Liang Wang, Qiang Xu, Michael Opoku Agyeman, Paris Kitsos (Editor)

Research output: Contribution to Book/ReportChapterpeer-review


The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT
Original languageEnglish
Title of host publicationEuromicro Conference on Digital System Design (DSD) (2016)
Place of PublicationU.S.
ISBN (Print)9781509028160
Publication statusPublished - 30 Sep 2016


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