SlideAcross: a low-latency adaptive router for chip multi-processor

Wen Zong, Liang Wang, Qiang Xu, Michael Opoku Agyeman, Paris Kitsos (Editor)

Research output: Contribution to Book/Report typesChapter

Abstract

The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT
Original languageEnglish
Title of host publicationEuromicro Conference on Digital System Design (DSD) (2016)
Place of PublicationU.S.
PublisherIEEE
Pages115-122
ISBN (Print)9781509028160
DOIs
Publication statusPublished - 30 Sep 2016

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Routers
Communication
Pipelines

Cite this

Zong, W., Wang, L., Xu, Q., Opoku Agyeman, M., & Kitsos, P. (Ed.) (2016). SlideAcross: a low-latency adaptive router for chip multi-processor. In Euromicro Conference on Digital System Design (DSD) (2016) (pp. 115-122). U.S.: IEEE. https://doi.org/10.1109/DSD.2016.40
Zong, Wen ; Wang, Liang ; Xu, Qiang ; Opoku Agyeman, Michael ; Kitsos, Paris (Editor). / SlideAcross: a low-latency adaptive router for chip multi-processor. Euromicro Conference on Digital System Design (DSD) (2016). U.S. : IEEE, 2016. pp. 115-122
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abstract = "The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9{\%} in average compared to low-latency router SWIFT",
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Zong, W, Wang, L, Xu, Q, Opoku Agyeman, M & Kitsos, P (ed.) 2016, SlideAcross: a low-latency adaptive router for chip multi-processor. in Euromicro Conference on Digital System Design (DSD) (2016). IEEE, U.S., pp. 115-122. https://doi.org/10.1109/DSD.2016.40

SlideAcross: a low-latency adaptive router for chip multi-processor. / Zong, Wen; Wang, Liang; Xu, Qiang; Opoku Agyeman, Michael; Kitsos, Paris (Editor).

Euromicro Conference on Digital System Design (DSD) (2016). U.S. : IEEE, 2016. p. 115-122.

Research output: Contribution to Book/Report typesChapter

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AU - Opoku Agyeman, Michael

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AB - The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT

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M3 - Chapter

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BT - Euromicro Conference on Digital System Design (DSD) (2016)

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Zong W, Wang L, Xu Q, Opoku Agyeman M, Kitsos P, (ed.). SlideAcross: a low-latency adaptive router for chip multi-processor. In Euromicro Conference on Digital System Design (DSD) (2016). U.S.: IEEE. 2016. p. 115-122 https://doi.org/10.1109/DSD.2016.40