TY - CHAP
T1 - A survey of recent contributions on low power NoC architectures
AU - Ofori-Attah, Emmanuel
AU - Agyeman, Michael Opoku
PY - 2018/1/8
Y1 - 2018/1/8
N2 - —The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by making adjustments to the elements in routers. The architecture itself and the Links. This paper will entail a survey conducted on recent contributions on NoC. As well as the techniques employed by researchers towards the reduction of power in the router architecture, network architecture and the links.
AB - —The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by making adjustments to the elements in routers. The architecture itself and the Links. This paper will entail a survey conducted on recent contributions on NoC. As well as the techniques employed by researchers towards the reduction of power in the router architecture, network architecture and the links.
KW - Network-on-chip
KW - Virtual channel sharing
KW - communication links NoC
KW - formatting
KW - low power router architecture
UR - http://www.mendeley.com/research/survey-recent-contributions-low-power-noc-architectures
U2 - 10.1109/SAI.2017.8252226
DO - 10.1109/SAI.2017.8252226
M3 - Chapter
SN - 9781509054435
T3 - Proceedings of Computing Conference 2017
SP - 1086
EP - 1090
BT - Proceedings of Computing Conference 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -