A survey of recent contributions on low power NoC architectures

Emmanuel Ofori-Attah, Michael Opoku Agyeman

Research output: Contribution to Book/ReportChapterpeer-review


—The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by making adjustments to the elements in routers. The architecture itself and the Links. This paper will entail a survey conducted on recent contributions on NoC. As well as the techniques employed by researchers towards the reduction of power in the router architecture, network architecture and the links.
Original languageEnglish
Title of host publicationProceedings of Computing Conference 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages5
ISBN (Print)9781509054435
Publication statusPublished - 8 Jan 2018

Publication series

NameProceedings of Computing Conference 2017


  • Network-on-chip
  • Virtual channel sharing
  • communication links NoC
  • formatting
  • low power router architecture


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