An Overview of On-Chip Cache Coherence Protocols

Zainab Al-Waisi, Michael Opoku Agyeman

Research output: Contribution to Book/ReportConference Contribution

Abstract

Cache coherence protocols play an important role in the performance of distributed and centralized shared-memory of a multiprocessor, and it they are required for maintaining data consistency in a chip-multiprocessor system (CMP). Thus, cache protocols play a major role in improving the performance of multiprocessor systems. Specifically, an efficient cache coherence protocol should ensure the updating of processor data, broadcasting valid data to all other processors and main memory to prevent the main memory or other processors from loading invalid values. To address this issue of efficiency in maintaining cache coherency, several contribution, such as using Invalidation-based protocols with a write through cache coherence, have been made over the past years. This paper presents an overview of emerging cache coherence protocols which aim at improving the performance of CMPs. Furthermore, an example of using an Invalidation-based protocol with a write through for solving cache’s coherency is provided.
Original languageEnglish
Title of host publication2017 Intelligent Systems Conference (IntelliSys)
Place of PublicationLondon
PublisherIEEE
Pages304-309
Number of pages6
ISBN (Electronic)978-1-5090-6435-9
ISBN (Print)978-1-5090-6436-6
DOIs
Publication statusPublished - 26 Mar 2018
EventIntelligent Systems Conference 2017 - London, United Kingdom
Duration: 7 Sep 20178 Sep 2017

Conference

ConferenceIntelligent Systems Conference 2017
Country/TerritoryUnited Kingdom
CityLondon
Period7/09/178/09/17

Keywords

  • Cache coherence
  • cache coherence protocols
  • invalidation-based protocol
  • update-based protocol
  • MSI
  • MESI
  • Dragon
  • Firefly protocol

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