An overview of on-chip cache coherence protocols

Zainab Al-Waisi, Michael Opoku Agyeman

Research output: Contribution to Book/ReportChapter


Cache coherence protocols play an important role in the performance of distributed and centralized shared-memory of a multiprocessor, and it they are required for maintaining data consistency in a chip-multiprocessor system (CMP). Thus, cache protocols play a major role in improving the performance of multiprocessor systems. Specifically, an efficient cache coherence protocol should ensure the updating of processor data, broadcasting valid data to all other processors and main memory to prevent the main memory or other processors from loading invalid values. To address this issue of efficiency in maintaining cache coherency, several contribution, such as using Invalidation-based protocols with a write through cache coherence, have been made over the past years. This paper presents an overview of emerging cache coherence protocols which aim at improving the performance of CMPs. Furthermore, an example of using an Invalidation-based protocol with a write through for solving cache’s coherency is provided.
Original languageEnglish
Title of host publicationIEEE IntelliSys Conference 2017 Proceedings
Place of PublicationLondon
Publication statusAccepted/In press - 15 Jan 2017


  • Cache coherence
  • cache coherence protocols
  • invalidation-based protocol
  • update-based protocol
  • MSI
  • MESI
  • Dragon
  • Firefly protocol

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    Al-Waisi, Z., & Opoku Agyeman, M. (Accepted/In press). An overview of on-chip cache coherence protocols. In IEEE IntelliSys Conference 2017 Proceedings IEEE.