Recently, hybrid wired-wireless Network-on-Chip (WiNoC) have been proposed to meet the performance and scalability demands of modern System-on-Chip (SoC) design. However, due to the presence of wirelines with multi-hop nodes in the hybrid architecture, WiNoCs have reduced performance efficiency. In this paper, we propose a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation in such emerging hybrid NoCs. The proposed router employs both dimension-ordered routing (DoR) and a deadlock free adaptive routing to transmit flits at low-loads and high traffic loads, respectively, to efficiently balance traffic in WiNoCs. By reducing the latency between the wired nodes and the wireless nodes, the proposed router can improve performance efficiency in terms of average packet delay by an average of 50% in WiNoCs.
|Title of host publication||NoCArc'16 Proceedings of the 9th International Workshop on Network on Chip Architectures|
|Place of Publication||New York|
|Publisher||Association for Computing Machinery (ACM)|
|Number of pages||56|
|Publication status||Published - 31 Oct 2016|
- Router architecture
- hybrid wired-wireless Network-on-Chip